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high speed mosfet driver absolute maximum ratings thermal characteristics speci?cations ? typical applications ? mosfet drivers ? switch mode power ampli?ers ? digital output ampli?ers ? pulse generators ? laser diode drivers ? ultrasound transducer drivers ? acoustic optical modulators features ? switching frequency: dc to 30mhz ? switching speeds 3-4ns 50? load ? low pulse width distortion ? single power supply ? 3v cmos schmitt trigger input 1v hysteresis ? output capable of 8a rms ? power dissipation capability >100w unit v unit c/w c w unit v a v ns a a pf v ns ratings 18 5.5 min typ max 0.71 175 >100 210 min typ max 8 18 8 3 1.8 2.2 8 1.2 200 8 2500 3 0.8 1.0 1.9 2.2 38 parameter supply voltage input single voltage characteristic junction to case thermal resistance operating junction temperature maximum power dissipation total power dissipation @ t c = 25c parameter supply voltage output current input voltage input voltage rising edge input voltage falling edge quiescent current max output current output capacitance input capacitance input low input high time delay (throughput) symbol v dd v in symbol r jc t j p d p dc symbol v dd i out 5 v in v in(r) 6 v in(f) 6 i ddq i o c oss c iss v il v ih v dly vdd vdd DRF100 15v, 8a, 30mhz the DRF100 is a high-speed power mosfet driver with a unique anti-ring function. it is intended to drive the gate of a power mosfet 3nf, gate capacitance to an 18v maximum, at frequencies up to 30mhz. it can produce output currents 8a rms, while dissipating 100w. 050-4912 rev a 2-2006 apt website - http://www.advancedpower.com
a simpli?ed DRF100 circuit diagram is illustrated above. by including the driver high speed by-pass capacitors (c1- c8), their contribution to the internal parasitic loop inductance of the driver output is greatly reduced. this, coupled with the tight geometry of the hybrid, allows optimum drive to the gate of the mosfet. this low parasitic approach, coupled with the schmitt trigger input, kelvin signal ground (4,5) and the anti-ring function, provide improved stability and control in kilowatt to multi-kilowatt, high frequency applications the in pin (4) is applied to a schmitt trigger. the signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed speci?cally for ring abatement. the p channel and n channel power drivers provide the high current to the out pin (9). the function, fn, pin (3) is used to disable the anti-ring function. it is recommended that the device be operated with this function enabled. func. = hi (+5v or float) anti-ring on, func. = low (0v or gnd.) anti-ring off. driver control logic in (4) highdriver output (9) low in (4) lowdriver output (9) high figure 1, DRF100 simpli?ed ciruit diagram driver speci?cations t j = 25c unless otherwise speci?ed driver output characteristics t j = 25c unless otherwise speci?ed test curcuit show on page 3. all measurements were made with the anti-ring circuit activated unless noted. 1. symmetry is the percent difference in high and low fwhm times with a 50% duty cycle square wave input. 2 r l = 50?, c l = 3000pf 3 10% - 90% see test circuit 4 50% - 50%, see test circuit 5 v dd = 18v, c l = 3000pf, f = 10mhz 6 performance speci?ed with this input. apt reserves the right to change, without notice, the speci?cations and information contained herein. unit ns % unit pf ? nh mhz min typical max 3.1 7.5 2.8 7.5 33 38 1.2 rl cl min typ max 2500 1 2 3 4 30 test conditions 15v dd 15v dd 15v 15v dd 3 parameter rise time 2,3 fall time 2,3 prop. delay 2,4 symmetry 1 parameter output capacitance 2,5 output resistance 2,5 output inductance 2,5 operating frequency symbol t r t f t d symbol c out r out l out f max 050-4912 rev a 2-2006 DRF100
the test circuit illustrated above was used to evaluate the DRF100 (available as an evaluation board drf-100eval). the input control signal is applied to the DRF100 via the in(4) and sg(5) pins via rg188. this provides excellent noise immunity and control of the signal ground currents. the fn pin is off and unwanted signals can cause erratic behavior, therefore fn pin is heavily by-passed on the evaluation board, see fn (3) above. the +vcc inputs (2,6) are heavily by-passed (c1-c3, c5-c7), this is in addition to the internal bypassing mentioned previously. the capacitors used for this function must be capable of supporting the rms currents and frequency of the load. figure 2, test circuit 050-4912 rev a 2-2006 DRF100
figure 3, leading edge throughput delay ~ 32ns = figure 4, trailing edge throughput delay ~ 33ns = figure 5, 30mhz output into 50? figure 6, output rise time = 2.8ns figure 7, output fall time = 2.0ns all waveforms on this page, figures 3 thru 7, were taken using the test circuit of figure 1, with the following test conditions: 1. +v dd = 15v 2. control input 5.0v/50? 3. load = 50? 050-4912 rev a 2-2006 DRF100
figure 8, leading edge throughput delay ~ 37ns = figure 9, trailing edge throughput delay ~ 37ns = figure 10, output rise time = 7.2ns figure 11, output fall time = 7.2ns figure 12, drf-100 output @ 30mhz in to 50? +3nf all waveforms on this page, figures 8 thru 12, were taken using the test circuit of figure 3, with the following test conditions: 4. +vdd = 15v 5. control input 5.0v/50? 6. load = 50?+3nf 050-4912 rev a 2-2006 DRF100
figure 13, anti-ring on figure 14, anit-ring off figure 15, anti-ring on figure 16, anit-ring off the output waveform with the anti-ring function on is illustrated in figure 13 and the anti-ring function off is illustrated in figure 14. the load is 50? with no load capacitance, other than the output capacitance of the driver. the output waveform with the anti-ring function on is illustrated in figure 15 and the anti-ring function off is illustrated in figure 16. the load is 50? + 3nf of capacitance. the ring amplitude in figure 15 is clearly above the 2-4v threshold voltage of most power mosfets, while in figure 16 we see that the ring peak is at ~ 2v, also see figure 13. it is most likely that the wave form of figure 16 will cause a cross conduction in a bridge or push pull topology. = 050-4912 rev a 2-2006 DRF100
t 1 t 2 t 3 t 4 a b c t 1 t 2 t 3 t 4 a b c figure 17 the real time gating of the fn function is illustrated in figure 17. at t 1 the fn trace ( c ) is deactivated and at t 4 it is reactivated. the output is shown as trace ( b ), there is signi?cant ringing on both the leading and tailing edges. trace ( a ) is the input control signal figure 18 in figure 18, trace ( b ) shows the anti- ring function active during the pulse. in trace ( b ) we see the output with a greatly reduced ring amplitude. note: load = 50? + 3nf, series induc - tance is estimated at 3nh. a typical mosfet can exceed this value. 050-4912 rev a 2-2006
t 1 t 2 t 3 t 4 a b c t 1 t 2 t 3 t 4 a b c in figure 19, we see the anti-ring func - tion fn active for the leading edge only, t 2 . figure 20, illustrates the anti-ring function active on the trailing edge only. note: load = 50? + 3nf, series induc - tance is estimated at 3 nh, a typical mosfet can exceed this value. figure 19 figure 20 050-4912 rev a 2-2006
vdd vdd figure 21, DRF100 mechanical outline 050-4912 rev a 2-2006 DRF100
+v dd b y-p ass l f +v dd by -p ass hf r2 5 0 ? i nput t er mi na ti on f n i nput thi s se c ti on c onf i gur ed b y us er figure 22, DRF100 eval board the dfr100 is a high power device and must have adequate cooling for full power operation evaluation boards are provided to facilitate the circuit design process by allowing the end user to quickly evaluate the performance of our components under a speci?c and single set of conditions. they are not intended to be used as a sub assembly in any ?nal product(s). care has been taken to insure that the evaluation boards are assembled to correctly represent the test circuit included in the component data sheet. there is no warranty of these evaluation boards beyond workmanship and materials. 050-4912 rev a 2-2006 DRF100
4.936 5.25 3.196 1.425 .716 1.7 0.900 advanced power technology DRF100 re 12/06/05 revd 3.50 see DRF100 mechanical drawing for physical dimension details pcb material - .062 fr4 4 holes .150 dia. figure 23, DRF100 eval board mechanical 050-4912 rev a 2-2006 DRF100
mounting instructions for flangeless packages heat sink mounting of any device in the flangeless package family follows the same process details outlined in this document. heat sink surface: 1. the heat sink surface should be smooth, free of nicks and burs; in addition it should be ?at to .001in./in tir, (total indicator run out) and be ?nished to ~ 68 cla, (center line average). 2. must be free of solder balls, metal shavings and any foreign objects or material. device preparation: 1. the leads should be prepared with an s bend, as shown in figure 25 prior to mounting on the heat sink. 2. the beo surface of the device must be free of any foreign objects or material. 3. the beo surface must be coated with a thin and uniform ?lm of thermal compound. 4. for commercial manufacturing the suggested method for thermal compound application is to apply the compound using a screen printer. this process insures con - sistent and repeatable performance with minimum effort. mechanical attachment: 1. the four screws (1-2-3-4), as shown in figure 24, should be installed and seated, then torqued to one-half the speci?cation, in the sequence shown. first screw 1 then screw 2, 3 and 4. 2. then complete the process by tighten - ing to the full speci?cation in the same manner. 3. the torque spec is 8in.lb. 1lb. (0.9nm) lead attachment: 1. the leads may now be soldered to the pcb 2. maximum lead temperature must not exceed 300oc for 10s. 3. for lead free use 96.5 % tin, 3% silver, and 0.5% copper. 4. non-lead free use 2% silver, 62% tin, 36% lead (sn62). figure 24, top and side view of a t3 device figure 25, stress relief bend 050-4912 rev a 2-2006 DRF100

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